OpenAI is pairing its custom-built Jalapeno inference chip with AMD's EPYC 'Turin' processors as the host silicon for its rack-scale AI systems — and deliberately not with Nvidia's competing Vera CPUs, according to a new report.
Tom's Hardware reported that each host tray in OpenAI's Jalapeno deployment carries two AMD EPYC Turin-class processors along with 1.5TB of DRAM, citing an interview with Richard Ho, OpenAI's vice president and head of hardware.
Maturity over marketing
Ho framed the choice of AMD as a pragmatic de-risking decision. Asked about Nvidia's Vera standalone CPU as an alternative host, he said it was "a little bit behind… on that maturity level" for OpenAI's current scale — a notable public judgment from a company that remains one of Nvidia's biggest customers.
The architecture splits the work across two racks: a CPU host rack with 16 'Katsu' trays and an accelerator rack with 16 'Vindaloo' trays holding 128 Jalapeno chips, stitched together by eight 'Chana' switch trays. OpenAI's figures put the paired system at roughly 160 kilowatts — 31kW for the host layer and 130kW for the accelerators — and claim 1.5 to 1.9 times more AI operations per watt and 1.7 to 3.6 times lower end-to-end latency than baselines on GPT-OSS 120B and DeepSeek R1 670B. The design is meant to scale to 16 racks and up to 2,048 Jalapeno accelerators.
Built with Broadcom, deploying late 2026
OpenAI partnered with Broadcom on silicon implementation and Celestica on system design. The Jalapeno chip taped out in November 2025, with initial deployments planned for late 2026.
The host decision matters because accelerators rarely work alone: production inference needs tokenisation, request handling, storage access, networking and orchestration — all CPU-bound work where a weak host can leave expensive accelerators idling. OpenAI needed a host platform with memory capacity, software compatibility and operational history, and Turin offered those without adding another immature component to the programme.
Sources:
OpenAI Pairs Jalapeno ASIC With AMD Turin, Skips Nvidia Vera — AI Weekly (via Tom's Hardware)
OpenAI Jalapeno ASIC Deployment Chooses AMD Turin, Not Nvidia Vera — Remio
Tom's Hardware reported that each host tray in OpenAI's Jalapeno deployment carries two AMD EPYC Turin-class processors along with 1.5TB of DRAM, citing an interview with Richard Ho, OpenAI's vice president and head of hardware.
Maturity over marketing
Ho framed the choice of AMD as a pragmatic de-risking decision. Asked about Nvidia's Vera standalone CPU as an alternative host, he said it was "a little bit behind… on that maturity level" for OpenAI's current scale — a notable public judgment from a company that remains one of Nvidia's biggest customers.
The architecture splits the work across two racks: a CPU host rack with 16 'Katsu' trays and an accelerator rack with 16 'Vindaloo' trays holding 128 Jalapeno chips, stitched together by eight 'Chana' switch trays. OpenAI's figures put the paired system at roughly 160 kilowatts — 31kW for the host layer and 130kW for the accelerators — and claim 1.5 to 1.9 times more AI operations per watt and 1.7 to 3.6 times lower end-to-end latency than baselines on GPT-OSS 120B and DeepSeek R1 670B. The design is meant to scale to 16 racks and up to 2,048 Jalapeno accelerators.
Built with Broadcom, deploying late 2026
OpenAI partnered with Broadcom on silicon implementation and Celestica on system design. The Jalapeno chip taped out in November 2025, with initial deployments planned for late 2026.
The host decision matters because accelerators rarely work alone: production inference needs tokenisation, request handling, storage access, networking and orchestration — all CPU-bound work where a weak host can leave expensive accelerators idling. OpenAI needed a host platform with memory capacity, software compatibility and operational history, and Turin offered those without adding another immature component to the programme.
Sources:
OpenAI Pairs Jalapeno ASIC With AMD Turin, Skips Nvidia Vera — AI Weekly (via Tom's Hardware)
OpenAI Jalapeno ASIC Deployment Chooses AMD Turin, Not Nvidia Vera — Remio
